1. Filed of the Invention
The present invention relates to a semiconductor device and its manufacturing method, especially a field effect transistor (hereinafter, also referred to as “FET”) and its manufacturing method.
2. Description of the Related Art
For example, in InAlAs/InGaAs heterostructure FET, a mesa structure sometimes is employed for device isolation. In this case, if an InGaAs channel layer comes in contact with a gate electrode, gate leakage current is generated, and the performance of the device becomes dramatically degraded. As a structure to prevent the gate electrode's contacting with a sidewall formed for device isolation and InGaAs channel layer exposed from the sidewall, a constitution is known in which a recess is formed between the gate electrode and the InGaAs channel layer by selectively etching only the InGaAs channel layer (See S. R. Bahl and J. A. Alamo “Elimination of Mesa-Sidewall Gate Leakage in InAlAs/InGaAs Heterostructures by Selective Sidewall Recessing.”, IEEE Electron Device Lett., Vol. 13, No. 4, p. 195, 1992).
In FET having InAlAs/InGaAs heterostructure and a mesa structure for device isolation, in order to prevent the gate electrode's coming in contact with InGaAs channel layer exposed from the mesa structure, a constitution is known, in which an air-bridge is formed between the gate electrode and the InGaAs channel layer by selectively etching only the InGaAs channel layer (See A. Fathimulla, J. Abrahams, T. Loughan and H. Hier, “High-Performance InAlAs/InGaAs HEMT's and MESFET's”, IEEE Electron Device Lett., Vol. 9, No. 7, p. 328, 1988).
For performing device isolation, in order to prevent the generation of gate leakage current by avoiding the exposure of the InGaAs channel layer using a planar FET structure, constitution is known in which all the regions other than an active region is made semiinsulating by ion implantation, in place of forming a mesa structure which has a concern of increase of gate leakage current due to a contact between the InGaAs channel layer and the gate electrode (See A. S. Brown et al., “Low-Temperature Buffer AlInAs/GaInAs on Inp HEMT Technology for Ultra-high-speed Integrated Circuits,” in Proc. IEEE GaAs IC Symp. 1989, p. 143).
In addition, another constitution is known, in which the InGaAs channel and the gate electrode are isolated from each other by forming a mesa structure for device isolation and then performing ion implantation onto the sidewall where the InGaAs channel layer is exposed from the mesa structure (See JP 08-279520).
For example, according to Bahl et al., the etchant used in the etching process for recessing remains in the recess between the gate electrode and the InGaAs channel layer. Since this remaining etchant usually contains an oxidizer such as hydrogen peroxide, it will oxidize the InAlAs layer which supplies electrons, so that the reliability of operation of the FET becomes reduced.
According to Fathimulla et al., since an air-bridge is formed after forming the gate electrode, etching has to be done right under the gate electrode while the gate electrode is exposed. Generally, if a semiconductor layer is etched while a gate electrode made of metal is exposed, the semiconductor layer will be abnormally etched due to a “battery effect” phenomenon. As a result characteristics of FET become degraded.
According to Brown et al., it is difficult to achieve satisfactory isolation characteristics by making all the regions other than the active region semiinsulating, in view of the band gap width.
As described above, in a field effect transistor having a mesa structure for device isolation, a constitution to effectively prevent generation of gate leakage current due to low Schottky barrier is not still realized.